View ICS8432DY-101T_1253032.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Integrated Circuit Systems, Inc.
ICS8432-101
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
FEATURES
* Dual differential 3.3V LVPECL outputs * Selectable CLK, nCLK or LVCMOS/LVTTL TEST_CLK * TEST_CLK can accept the following input levels: LVCMOS or LVTTL * CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL * CLK, nCLK or TEST_CLK maximum input frequency: 40MHz * Output frequency range: 25MHz to 700MHz * VCO range: 250MHz to 700MHz * Accepts any single-ended input signal on CLK input with resistor bias on nCLK input * Parallel interface for programming counter and output dividers * RMS period jitter: 5ps (maximum) * Cycle-to-cycle jitter: 25ps (maximum) * 3.3V supply voltage * 0C to 70C ambient operating temperature * Lead-Free package fully RoHS compliant
GENERAL DESCRIPTION
The ICS8432-101 is a general purpose, dual output Differential-to-3.3V LVPECL high frequency HiPerClockSTM synthesizer and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8432-101 has a selectable TEST_CLK or CLK, nCLK inputs. The TEST_CLK input accepts LVCMOS or LVTTL input levels and translates them to 3.3V LVPECL levels. The CLK, nCLK pair can accept most standard differential input levels. The VCO operates at a frequency range of 250MHz to 700MHz. The VCO frequency is programmed in steps equal to the value of the input differential or single ended reference frequency. The VCO and output frequency can be programmed using the serial or parallel interfaces to the configuration logic. The low phase noise characteristics of the ICS8432-101 makes it an ideal clock source for Gigabit Ethernet and SONET applications.
ICS
BLOCK DIAGRAM
VCO_SEL CLK_SEL TEST_CLK CLK nCLK 0
PIN ASSIGNMENT
VCO_SEL nP_LOAD nCLK M4 M3 M2 M1 M0
32 31 30 29 28 27 26 25 1 M5 M6 M7 M8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TEST VCC FOUT1 nFOUT1 VCCO FOUT0 nFOUT0 VEE
24 23 22
CLK TEST_CLK CLK_SEL VCCA S_LOAD S_DATA S_CLOCK MR
PLL
PHASE DETECTOR MR /M VCO 0 1 /1 /2 /4 /8 FOUT0 nFOUT0 FOUT1 nFOUT1
N0 N1 nc VEE
ICS8432-101
21 20 19 18 17
S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 N0:N1
CONFIGURATION INTERFACE LOGIC
TEST
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
8432DY-101
www.icst.com/products/hiperclocks.html
1
REV. B JUNE 1, 2005
Integrated Circuit Systems, Inc.
ICS8432-101
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
rial event occurs. As a result, the M and N bits can be hardwired to set the M divider and N output divider to a specific default state that will automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the input frequency and the M divider is defined as follows: fVCO = fIN x M The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 25MHz reference are defined as 8 M 28. The frequency out is defined as follows: fOUT = fVCO = fIN x M N N Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows: T1 0 0 1 1 T0 0 1 0 1 TEST Output LOW S_Data, Shift Register Input Output of M divider CMOS Fout
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation using a 25MHz clock input. Valid PLL loop divider values for different input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1.
The ICS8432-101 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A differential clock input is used as the input to the ICS8432-101. This input is fed into the phase detector. A 25MHz clock input provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of 250MHz to 700MHz. The output of the M divider is also applied to the phase detector. The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note, that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. The programmable features of the ICS8432-101 support two input modes to program the PLL M divider and N output divider. The two input operational modes are parallel and serial. Figure1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a se-
SERIAL LOADING
S_CLOCK
S_DATA
T1
T0
H
*NULL
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
S_LOAD
S
t
nP_LOAD
t
S
PARALLEL LOADING
M0:M8, N0:N1 nP_LOAD
M, N
t
S_LOAD
S
t
H
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
*NOTE:
8432DY-101
The NULL timing slot must be observed.
www.icst.com/products/hiperclocks.html
2
REV. B JUNE 1, 2005
Integrated Circuit Systems, Inc.
ICS8432-101
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Type Input Input Input Unused Power Output Power Output Power Output Pullup M divider inputs. Data latched on LOW-to-HIGH transistion Pulldown of nP_LOAD input. LVCMOS / LVTTL interface levels. Pulldown Determines output divider value as defined in Table 3C, Function Table. LVCMOS / LVTTL interface levels. No connect. Negative supply pins. Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS / LVTTL interface levels. Core supply pin. Differential output for the synthesizer. 3.3V LVPECL interface levels. Output supply pin. Differential output for the synthesizer. 3.3V LVPECL interface levels. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs FOUTx to go low and the inver ted outputs nFOUTx to go high. When logic LOW, the internal dividers and the outputs are enabled. Asser tion of MR does not affect loaded M, N, and T values. LVCMOS / LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Shift register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Controls transition of data from shift register into the dividers. LVCMOS / LVTTL interface levels. Analog supply pin. Clock select input. Selects between differential clock input or TEST_CLK input as the PLL reference source. When HIGH, selects CLK, nCLK inputs. When LOW, selects TEST_CLK input. LVCMOS / LVTTL interface levels. Test clock input. LVCMOS / LVTTL interface levels. Non-inver ting differential clock input. Description
TABLE 1. PIN DESCRIPTIONS
Number 1 2, 3, 4 28, 29 30, 31, 32 5, 6 7 8, 16 9 10 11, 12 13 14, 15 Name M5 M6, M7, M8, M0, M1, M2, M3, M4 N0, N1 nc VEE TEST VCC FOUT1, nFOUT1 VCCO FOUT0, nFOUT0
17
MR
Input
Pulldown
18 19 20 21 22 23 24 25 26 27
S_CLOCK S_DATA S_LOAD VCCA CLK_SEL TEST_CLK CLK nCLK nP_LOAD VCO_SEL
Input Input Input Power Input Input Input Input Input Input
Pulldown Pulldown Pulldown
Pullup Pulldown Pulldown Pullup
Inver ting differential clock input. Parallel load input. Determines when data present at M8:M0 is Pulldown loaded into M divider, and when data present at N1:N0 sets the N output divider value. LVCMOS / LVTTL interface levels. Determines whether synthesizer is in PLL or bypass mode. Pullup LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characterisitics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN
8432DY-101
Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor
Test Conditions
Minimum
Typical 4 51 51
Maximum
Units pF k k
www.icst.com/products/hiperclocks.html
3
REV. B JUNE 1, 2005
Integrated Circuit Systems, Inc.
ICS8432-101
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 3A. PARALLEL
AND
SERIAL MODE FUNCTION TABLE
Inputs Conditions S_CLOCK X X X L L X S_DATA X X X Data Data Data X Data Reset. Forces outputs LOW. Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N output divider. M divider and N output divider values are latched. Parallel or serial inputs do not affect shift registers. S_DATA passed directly to M divider as it is clocked. X X L L L H
MR H L L L L L L
nP_LOAD X L H H H H
M X Data Data X X X X
N X Data Data X X X X
S_LOAD
L H X X NOTE: L = LOW H = HIGH X = Don't care = Rising edge transition = Falling edge transition
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
VCO Frequency (MHz) 200 225 250 275 * * 650 675 M Divide 8 9 10 11 * * 26 27 256 M8 0 0 0 0 * * 0 0 128 M7 0 0 0 0 * * 0 0 64 M6 0 0 0 0 * * 0 0 32 M5 0 0 0 0 * * 0 0 16 M4 0 0 0 0 * * 1 1 8 M3 1 1 1 1 * * 1 1 4 M2 0 0 0 0 * * 0 0 2 M1 0 0 1 1 * * 1 1 1 M0 0 1 0 1 * * 0 1
700 28 0 0 0 0 1 1 1 0 0 NOTE 1: These M divide values and the resulting frequencies correspond to differential input or TEST_CLK input frequency of 25MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs N1 0 0 1 1 N0 0 1 0 1 N Divider Value 1 2 4 8 Output Frequency (MHz) Minimum 250 125 62.5 31.25 Maximum 700 350 175 87.5
8432DY-101
www.icst.com/products/hiperclocks.html
4
REV. B JUNE 1, 2005
Integrated Circuit Systems, Inc.
ICS8432-101
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
4.6V -0.5V to VCC + 0.5 V 50mA 100mA 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VCC VCCA VCCO IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3. 3 3. 3 3.3 Maximum 3.465 3.465 3.465 120 15 Units V V V mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter Input High Voltage VCO_SEL, CLK_SEL, MR, S_LOAD, S_DATA, S_CLOCK, nP_LOAD, M0:M8, N0:N1 TEST_CLK VCO_SEL, CLK_SEL, MR, S_LOAD, S_DATA, S_CLOCK, nP_LOAD, M0:M8, N0:N1 TEST_CLK M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_DATA, S_LOAD, nP_LOAD M5, CLK_SEL, VCO_SEL M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_DATA, S_LOAD, nP_LOAD M5, CLK_SEL, VCO_SEL VOH VOL Output High Voltage Output Low Voltage TEST TEST Test Conditions Minimum 2 2 -0.3 -0.3 VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V VCC = 3.135V, IOH = -36mA VCC = 3.135V, IOL = 36mA -5 Typical Maximum VCC + 0.3 VCC + 0.3 0.8 1.3 150 5 Units V V V V A A A
VIH
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
-150 2.6 0.5
A V V
8432DY-101
www.icst.com/products/hiperclocks.html
5
REV. B JUNE 1, 2005
Integrated Circuit Systems, Inc.
ICS8432-101
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Test Conditions CLK nCLK CLK nCLK VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 0.15 1.3 VCC - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current
Peak-to-Peak Input Voltage
VCMR Common Mode Input Voltage VEE + 0.5 NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VOH VOL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 1.0 VCCO - 1.7 1.0 Units V V V
Peak-to-Peak Output Voltage Swing VSWING NOTE 1: Outputs terminated with 50 to VCCO - 2V.
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol fIN Parameter TEST_CLK; NOTE 1 Input Frequency CLK, nCLK; NOTE 1 Test Conditions Minimum 10 10 Typical Maximum 40 40 Units MHz MHz
S_CLOCK 40 MHz NOTE 1: For the differential input and TEST_CLK frequency range, the M value must be set for the VCO to operate within the 250MHz to 700MHz range. Using the minimum input frequency of 10MHz, valid values of M are 25 M 70. Using the maximum frequency of 40MHz, valid values of M are 7 M 17.
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter FOUT Output Frequency Cycle-to-Cycle Jitter ; NOTE 1 Period Jitter, RMS Output Skew; NOTE 1, 2 Output Rise/Fall Time M, N to nP_LOAD tS Setup Time S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to nP_LOAD tH odc tPW Hold Time S_DATA to S_CLOCK S_CLOCK to S_LOAD Output Duty Cycle Output Pulse Width N>1 N=1 20% to 80% 200 5 5 5 5 5 5 47 tPERIOD/2 - 150 53 tPERIOD/2 + 150 1 fVCO > 350MHz fOUT > 100MHz Test Conditions Minimum 31.25 Typical Maximum 700 25 5 15 700 Units MHz ps ps ps ps ns ns ns ns ns ns % ps ms
tjit(cc) tjit(per) tsk(o)
t R / tF
PLL Lock Time tLOCK See Parameter Measurement Information section. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points.
8432DY-101
www.icst.com/products/hiperclocks.html
6
REV. B JUNE 1, 2005
Integrated Circuit Systems, Inc.
ICS8432-101
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION
2V
VCC, VCCO
Qx
SCOPE
VCC
nCLK
LVPECL
nQx CLK
V
PP
Cross Points
V
CMR
VEE
V EE
-1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
VOH VREF VOL
DIFFERENTIAL INPUT LEVEL
nFOUTx FOUTx
tcycle
n
Reference Point
(Trigger Edge)
Histogram
tjit(cc) = tcycle n -tcycle n+1
1000 Cycles
Mean Period
(First edge after trigger)
PERIOD JITTER
CYCLE-TO-CYCLE JITTER
nFOUTx
80%
FOUTx nFOUTy FOUTy
Clock Outputs
20% tR tF
tsk(o)
OUTPUT SKEW
nFOUTx FOUTx
OUTPUT RISE/FALL TIME
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
8432DY-101
www.icst.com/products/hiperclocks.html
7
1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10-7)% of all measurements
tcycle n+1
80% VSW I N G 20%
REV. B JUNE 1, 2005
Integrated Circuit Systems, Inc.
ICS8432-101
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION
STORAGE AREA NETWORKS
A variety of technologies are used for interconnection of the elements within a SAN. The tables below list the common application frequencies as well as the ICS8432-101 configurations used to generate the appropriate frequency.
Table 7. Common SANs Application Frequencies
Interconnect Technology Gigabit Ethernet Fibre Channel Infiniband Clock Rate 1.25 GHz FC1 1.0625 GHz FC2 2.1250 GHz 2.5 GHz Reference Frequency to SERDES (MHz) 125, 250, 156.25 106.25, 53.125, 132.8125 125, 250 Crystal Frequency (MHz) 25, 19.53125 16.6015625, 25 25
Table 8. Configuration Details for SANs Applications
Interconnect Technology CLK, nCLK Input (MHz) 25 25 Gigabit Ethernet 25 19.53125 25 Fiber Channel 1 25 Fiber Channel 2 Infiniband 25 250 0 0 0 0 1 0 1 0 0 0 1 16.6015625 25 106.25 132.8125 125 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 1 0 0 0 1 0 0 1 1 1 0 0 0 156.25 156.25 53.125 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 1 ICS8432-101 Output Frequency to SERDES (MHz) 125 250 ICS8432-101 M & N Settings M8 M7 M6 M5 M4 M3 M2 0 0 0 0 0 0 0 0 1 1 0 0 1 1 M1 M0 0 0 0 0 N1 1 0 N0 0 1
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8432-101 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin.
8432DY-101
3.3V VCC .01F V CCA .01F 10 F 10
FIGURE 2. POWER SUPPLY FILTERING
REV. B JUNE 1, 2005
www.icst.com/products/hiperclocks.html
8
Integrated Circuit Systems, Inc.
ICS8432-101
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 3 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 3. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50 FOUT FIN
125 Zo = 50 FOUT
50 50 VCC - 2V RTT
125
Zo = 50
FIN
Zo = 50 84 84
RTT =
1 Z ((VOH + VOL) / (VCC - 2)) - 2 o
FIGURE 4A. LVPECL OUTPUT TERMINATION
8432DY-101
FIGURE 4B. LVPECL OUTPUT TERMINATION
REV. B JUNE 1, 2005
www.icst.com/products/hiperclocks.html
9
Integrated Circuit Systems, Inc.
ICS8432-101
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 5A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 5A to 5E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50 R3 50 LVPECL HiPerClockS Input R1 50 R2 50 Zo = 50 Ohm nCLK HiPerClockS Input CLK
FIGURE 5A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 5B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 5C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 5D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 125 R4 125 CLK Zo = 50 Ohm C2 nCLK HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 5E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
8432DY-101
BY
www.icst.com/products/hiperclocks.html
10
REV. B JUNE 1, 2005
Integrated Circuit Systems, Inc.
ICS8432-101
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P.C. board.
LAYOUT GUIDELINE
The schematic of the ICS8432-101 layout example used in this layout guideline is shown in Figure 6A. The ICS8432-101 recommended PCB board layout for this example is shown in Figure 6B. This layout example is used as a general guideline.
nCLK CLK 32 31 30 29 28 27 26 25 R7 VCC 10 24 23 22 21 20 19 18 17 C11 0.01u XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK MR C16 10u U1
TEST VDD FOUT1/2 nFOUT1/2 VCCO FOUT nFOUT VEE
1 2 3 4 5 6 7 8
M5 M6 M7 M8 N0 N1 nc VEE
M4 M3 M2 M1 M0 VCO_SEL nP_LOAD nCLK
CLK REF_IN nCLK_SEL VDDA S_LOAD S_DATA S_CLOCK MR
Termination A
VCC
VCC FOUT FOUTN
9 10 11 12 13 14 15 16
8432-101
Termination B (not shown in the layout)
IN+ IN-
TEST
R1 125 Zo = 50 Ohm IN+ TL1 Zo = 50 Ohm
R3 125
VCC
C14 0.1u
INC15 0.1u TL2 R2 84 R4 84
R2 50
R1 50
R3 50
FIGURE 6A. SCHEMATIC
OF
RECOMMENDED LAYOUT
8432DY-101
www.icst.com/products/hiperclocks.html
11
REV. B JUNE 1, 2005
Integrated Circuit Systems, Inc.
ICS8432-101
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
system failure. The trace shape and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. * The traces with 50 transmission lines TL1 and TL2 at FOUT and nFOUT should have equal delay and run adjacent to each other. Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. * Keep the clock trace on same layer. Whenever possible, avoid any vias on the clock traces. Any via on the trace can affect the trace characteristic impedance and hence degrade signal quality. * To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow more space between the clock trace and the other signal trace. * Make sure no other signal trace is routed between the clock trace pair. The matching termination resistors R1, R2, R3 and R4 should be located as close to the receiver input pins as possible. Other termination schemes can also be used but are not shown in this example.
The following component footprints are used in this layout example: All the resistors and capacitors are size 0603.
POWER
AND
GROUNDING
Place the decoupling capacitors C14 and C15 as close as possible to the power pins. If space allows, placing the decoupling capacitor at the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin generated by the via. Maximize the pad size of the power (ground) at the decoupling capacitor. Maximize the number of vias between power (ground) and the pads. This can reduce the inductance between the power (ground) plane and the component power (ground) pins. If VCCA shares the same power supply with VCC, insert the RC filter R7, C11, and C16 in between. Place this RC filter as close to the VCCA as possible.
CLOCK TRACES
AND
TERMINATION
The component placements, locations and orientations should be arranged to achieve the best clock signal quality. Poor clock signal quality can degrade the system performance or cause system failure. In the synchronous high-speed digital system, the clock signal is less tolerable to poor signal quality than other signals. Any ringing on the rising or falling edge or excessive ring back can cause
GND U1
PIN 1
C11 C16 VCCA R7 Close to the input pins of the receiver R4 R3 TL1N
TL1N
VCC VIA
C15 C14
TL1 R2
TL1 TL1, TL2 are 50 Ohm traces and equal length
R1
FIGURE 6B. PCB BOARD LAYOUT
FOR
ICS8432-101
8432DY-101
www.icst.com/products/hiperclocks.html
12
REV. B JUNE 1, 2005
Integrated Circuit Systems, Inc.
ICS8432-101
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8432-101. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS8432-101 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 120mA = 416mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30.2mW = 60.4mW
Total Power_MAX (3.465V, with all outputs switching) = 416mW + 60.4mW = 476.4mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 9 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.476W * 42.1C/W = 90C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 9. THERMAL RESISTANCE JA
FOR
32-PIN LQFP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8432DY-101
www.icst.com/products/hiperclocks.html
13
REV. B JUNE 1, 2005
Integrated Circuit Systems, Inc.
3. Calculations and Equations.
ICS8432-101
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7.
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CCO_MAX
- 1.0V
-V
OH_MAX
) = 1.0V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CCO_MAX
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO_MAX
-V
OH_MAX
)=
[(2V - 1V)/50] * 1V = 20.0mW
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
))/R ] * (V
L
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
8432DY-101
www.icst.com/products/hiperclocks.html
14
REV. B JUNE 1, 2005
Integrated Circuit Systems, Inc.
ICS8432-101
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE 10. JAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8432-101 is: 3712
8432DY-101
www.icst.com/products/hiperclocks.html
15
REV. B JUNE 1, 2005
Integrated Circuit Systems, Inc.
ICS8432-101
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
32 LEAD LQFP
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 11. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc
Reference Document: JEDEC Publication 95, MS-026
8432DY-101
MINIMUM
NOMINAL 32
MAXIMUM
1.60 0.05 1.35 0.30 0.09 9.00 BASIC 7.00 BASIC 5.60 9.00 BASIC 7.00 BASIC 5.60 0.80 BASIC 0.45 0 0.60 0.75 7 0.10
www.icst.com/products/hiperclocks.html
16
REV. B JUNE 1, 2005
0.15 1.40 0.37 1.45 0.45 0.20
Integrated Circuit Systems, Inc.
ICS8432-101
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Marking Package 32 Lead LQFP 32 Lead LQFP 32 Lead "Lead-Free" LQFP 32 Lead "Lead-Free" LQFP Shipping Packaging tray 1000 tape & reel tray 1000 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 12. ORDERING INFORMATION
Part/Order Number ICS8432DY-101 ICS8432DY-101T ICS8432DY-101LF ICS8432DY-101LFT ICS8432DY-101 ICS8432DY-101 TBD TB D
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8432DY-101
www.icst.com/products/hiperclocks.html
17
REV. B JUNE 1, 2005
Integrated Circuit Systems, Inc.
ICS8432-101
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
REVISION HISTORY SHEET Description of Change Features Section - added HCSL to input levels. Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical. Absolute Maximum Ratings - changed Output rating. Added Differential Clock Input Interface section. Test Output Table - changed last line from CMOS Fout/2 to CMOS Fout Changed VCO Frequency min. from 200MHz to 250MHz through data sheet. Updated Parallel & Serial Load Operations Diagram. Programmable Output Divider Function Table - changed minimum values. AC Table - changed FOUT min. from 25MHz to 31.25MHz. Updated LVPECL Output Termination Diagrams. Features Section - added Lead-Free bullet. Updated Fig. 1 Parallel & Serial Load Operations. AC Characteristics Table - deleted Note "Jitter performance using XTAL inputs". Ordering Information Table - added Lead-Free par t number. Date
Rev
Table T2
A
A
B
T3C T6
B
T6 T12
Page 1 3 5 10 2 1 2 4 6 9 1 2 6 17
7/8/03
7/23/03
9/5/03
6/1/05
8432DY-101
www.icst.com/products/hiperclocks.html
18
REV. B JUNE 1, 2005

▲Up To Search▲

Price & Availability of ICS8432DY-101T

	To Download ICS8432DY-101T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .